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1. Field of the Invention
This invention relates to digital to analog converter circuits, and particularly to those incorporating a sigma-delta modulator circuit, and more particularly to those suitable for use in a phase locked loop circuit.
2. Description of Problem to be Solved and Related Art
Phase locked loops (PLLs) have been known and studied for quite some time. Initially they were very expensive to implement, and found use in only the most technically-demanding and/or cost-insensitive applications. However, as the cost of integrated circuit technology has decreased over the years, and as the performance capability of such integrated circuit technology has increased, today PLLs are extremely inexpensive to implement and are found in wide use in many applications.
Within a traditional PLL, a filter block is frequently included to low-pass filter an output signal of a phase/frequency detector to generate a control signal for a voltage controlled oscillator (VCO) in order to influence the frequency (and hence the phase) of the VCO output signal. The filter block is often implemented using a charge pump and one or more loop filter capacitors, as is well known in the art. Such loop filter capacitors may be required to be very large for the PLL to exhibit acceptable peaking behavior in its frequency response.
Moreover, for certain applications, the loop bandwidth may need to be extremely low, including as low as 100 Hz. Achieving a bandwidth this low is very difficult using traditional techniques, and may require large capacitors which are difficult to integrate onto an integrated circuit without requiring large amounts of die area. For this reason, a loop filter capacitor is frequently provided externally. But such an external capacitor adds an additional complexity to board layout, and introduces noise susceptibility on the extremely critical loop filter node within the PLL.
Digital techniques for implementing a PLL loop filter may be utilized to digitally integrate a digital phase error signal to yield a digital signal representing the integrated phase error signal, and thereby reduce substantially the capacitors which must be integrated of are desired. But such a digital signal may still need to be converted to one or more analog signals to control a VCO. Improved digital-to-analog converter circuits (DAC) are still greatly desired.
A PLL incorporating a digital loop filter preferably includes one or more digital-to-analog converter circuits to convert a digital loop filter value to one or more control signals for controlling a controlled oscillator, such as a VCO. Preferably the one or more DACs include a hybrid first order/second order sigma-delta modulator to advantageously achieve the lower noise properties of a second order modulator, but also achieve full-scale output range of a first order modulator. When the analog output voltage of a DAC is at a value either at or near the top or bottom voltage rail (i.e., at or near the desired output range), the sigma-delta modulator is operated as a first order modulator to achieve a full-scale output range, but otherwise the sigma-delta modulator is configured to operate as a second order modulator to achieve the lower noise properties.
Accordingly, in one embodiment, the invention provides a digital-to-analog converter circuit incorporating a hybrid first order/second order sigma-delta modulator circuit. In some embodiments, the DAC may include a filter circuit coupled to the output of the sigma-delta modulator. In certain embodiments, the DAC may also include an NRZ-to-RZ coder circuit coupled between the output of the sigma-delta modulator and the filter circuit.